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dts: stm32h7rs: Add SDMMC support for STM32H7RS series #97293

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@bricle bricle commented Oct 9, 2025 •
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This PR adds SDMMC support for STM32H7RS series microcontrollers and enables it on two development boards.

Changes:

  • SoC support: Add SDMMC1 and SDMMC2 controller configurations for STM32H7RS series

    • Includes register addresses, clock sources, reset controls, and interrupt definitions

  • Board enablement: Configure SDMMC1 on supported boards:

    • ART-Pi2: 4-bit SD card interface with card detection
    • STM32H7S78-DK: 4-bit SD card interface with card detection

Clock Configuration:

Both boards use PLL2S as the kernel peripheral clock source:

  • PLL2S frequency: 150MHz
  • Clock divider: 15 (clk-div = 13 register value)
  • Resulting SDMMC clock: 10MHz

Hardware Features:

  • 4-bit bus width support
  • Card detection via GPIO

Testing Status:

  • ART-Pi2: Tested and verified working with zephyr/tests/drivers/disk/disk_performance:
*** Booting Zephyr OS build v4.2.0-2287-g5945a3fcd1eb ***
Running TESTSUITE disk_performance
===================================================================
Disk reports 124735488 sectors
Disk reports sector size 512
START - test_random_read
512 Byte IOPS over 64 random reads: 2354 IOPS
 PASS - test_random_read in 0.032 seconds
===================================================================
START - test_random_write
512 Byte IOPS over 64 random writes: 942 IOPS
 PASS - test_random_write in 0.218 seconds
===================================================================
START - test_sequential_read
Average read speed over one sector: 1081 KiB/s
Average read speed over 64 sectors: 2656 KiB/s
 PASS - test_sequential_read in 0.133 seconds
===================================================================
START - test_sequential_write
Average write speed over one sector: 481 KiB/s
Average write speed over 64 sectors: 2496 KiB/s
 PASS - test_sequential_write in 0.212 seconds
===================================================================
TESTSUITE disk_performance succeeded

------ TESTSUITE SUMMARY START ------

SUITE PASS - 100.00% [disk_performance]: pass = 4, fail = 0, skip = 0, total = 4 duration = 0.595 seconds
 - PASS - [disk_performance.test_random_read] duration = 0.032 seconds
 - PASS - [disk_performance.test_random_write] duration = 0.218 seconds
 - PASS - [disk_performance.test_sequential_read] duration = 0.133 seconds
 - PASS - [disk_performance.test_sequential_write] duration = 0.212 seconds

------ TESTSUITE SUMMARY END ------

===================================================================
PROJECT EXECUTION SUCCESSFUL
  • STM32H7S78-DK: Configuration based on hardware specifications (no physical board available for testing)

Note: I don't have access to the STM32H7S78-DK physical board, but the configuration should be correct based on the hardware documentation. If anyone could help test this board, it would be greatly appreciated, and I'm willing to make adjustments based on the test results.

bricle added 3 commits October 9, 2025 23:02
@bricle
dts: stm32: stm32h7rs: Add sdmmc1 and sdmmc2 configuration
cf59a9e 
Provide the soc configuration for sdmmc1 and sdmmc2 controllers.
This includes registers address, clocks, resets and interrupt line
details.

Signed-off-by: Shan Pen <[email protected]>
@bricle
boards: art_pi2: Add SDMMC1 configuration with PLL2 kernel clock
ab5dce7 
Configure SDMMC1 with 4-bit bus width and card detection. Use PLL2S
as kernel peripheral clock (150MHz) divided by 15 to achieve 10MHz
SDMMC clock with clk-div = <13>.

Signed-off-by: Shan Pen <[email protected]>
@bricle
boards: st: stm32h7s78_dk: Add PLL2 node and SDMMC1 node
44e3d05 
Configure SDMMC1 with 4-bit bus width and card detection. Use PLL2S
as kernel peripheral clock (150MHz) divided by 15 to achieve 10MHz
SDMMC clock with clk-div = <13>.

Signed-off-by: Shan Pen <[email protected]>
@bricle bricle mentioned this pull request Oct 9, 2025
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@bricle bricle marked this pull request as draft October 9, 2025 15:13
@bricle bricle closed this Oct 9, 2025
@bricle bricle reopened this Oct 9, 2025
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sonarqubecloud bot commented Oct 9, 2025

Quality Gate Passed Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

@bricle bricle marked this pull request as ready for review October 9, 2025 15:33
@bricle bricle force-pushed the stm32h7rs_sdmmc branch 2 times, most recently from 34aaab0 to 44e3d05 Compare October 9, 2025 15:34
etienne-lms
etienne-lms approved these changes Oct 9, 2025
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LGTM. Same state as #94965 last proposal.

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Ci build test error is unrelated:

/__w/zephyr/zephyr/subsys/usb/device_next/class/usbd_midi2.c: In function 'usbd_midi_send':
/__w/zephyr/zephyr/subsys/usb/device_next/class/usbd_midi2.c:472:17: error: format '%X' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Werror=format=]
  472 |         LOG_DBG("Send MT=%X group=%X", UMP_MT(ump), UMP_GROUP(ump));
      |                 ^~~~~~~~~~~~~~~~~~~~~
(snip)
/__w/zephyr/zephyr/subsys/usb/device_next/class/usbd_midi2.c:472:36: note: format string is defined here
  472 |         LOG_DBG("Send MT=%X group=%X", UMP_MT(ump), UMP_GROUP(ump));
      |                                   ~^
      |                                    |
      |                                    unsigned int
      |                                   %lX

It's related to commit 4b04b74 that uses BIT_MASK() in UMP_GROUP(ump) while BIT_MASK() defines an unsigned long mask value:

#define BIT_MASK(n) (BIT(n) - 1UL)

@etienne-lms etienne-lms mentioned this pull request Oct 9, 2025
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